Field
Implementations described herein generally relate to methods of selective deposition of metal silicide. More specifically, implementations described herein generally relate to methods of forming metal silicide nanowires for semiconductor applications.
Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually necessitates faster circuitry and greater circuit densities. The demand for greater circuit densities necessitates a reduction in the dimensions of the integrated circuit components.
Copper (Cu) interconnects have been used as a replacement for Aluminum (Al) for decades. The number of transistors formed on a substrate is reaching the multi-millions range packed in small areas consistent with Moore's law. As the number of transistors increases and the size of the transistors decreases, Cu resistivity is exponentially increasing once the metal line dimension approaches or gets below the Cu mean free path of 39 nanometers (“nm”).
The post copper era necessitates new interconnect materials that have low resistivity and narrower mean free path. The mean free path is the average distance traveled by a moving particle (such as an electron, an atom, or a photon) between successive impacts (collisions), which modify the direction or energy or other particle properties of the moving particle. Some metals already under investigation include cobalt (Co), tungsten (W), and some metal alloys. Silicides, such as Nickel Silicide (Ni—Si) interconnects and Cobalt Silicide (CoSi2) interconnects are strong potential candidates given the small mean free path of approximately 5 nm for Ni—Si. Even though Ni—Si resistivity is higher than Cu resistivity, the Ni—Si narrow mean free path of approximately 5 nm gives Ni—Si a strong advantage to replace Cu for advanced future technology nodes of 7 nm and below.
However, current processing methods are not amenable to direct device integration for the strong potential candidates. Most studies involving silicide nanowires have been done with freestanding nanowires, as current processing methods can lead to dielectric damage, thermal budget issues, lattice defects and other problems. Regarding thermal budget issues, low resistivity Ni—Si phase formation typically involves high anneal temperatures of greater than 650 degrees Celsius. These high anneal temperatures are not suitable in back-end-of-line (BEOL) integration, due in part to the temperature budget limitation (e.g., less than about 400 degrees Celsius) of most low-k materials. However, annealing Ni—Si at temperatures lower than 650 degrees Celsius leads to volume expansion of the Ni—Si and formation of high resistivity Ni—Si phases.
Therefore, there is a need for methods of forming low resistivity Ni—Si phase at low temperatures that are suitable for semiconductor manufacturing applications.